For faster operation speed of the memory, a configuration to divide a memory cell array is known. For example, a SRAM (Static Random Access Memory) which is one type of RAM is adopted as a structure to divide a memory cell array.
FIG. 12 is a block diagram of a conventional memory circuit. As depicted by FIG. 12, memory cells 102-0˜102-n of the memory circuit is divided into two memory cell blocks 100A and 100B. The first memory cell block 100A includes a memory cell 102-0˜102-m. The second memory cell block 100B includes a memory cell 102-m+1˜102-n. 
The memory control circuit 110 is provided between the memory cell blocks 100A and 100B. The memory control circuit 110 is provided one pair of write circuits 112 and 114 and a single read circuit 116. The write circuit 112 connects to the memory cell block 100A by a bit line blx_a and a bit line bl_a. In addition, the single read circuit 116 connects to two the memory cell blocks 100A. The read circuit 116 connects to the memory cell blocks 100A and 100B by the bit line bl_a and a bit line bl_b. Word selection signals WL0˜WLn select the memory cell 102-0˜102-n. 
The read circuit 116 uses a single-ended input circuit or a differential sense amplifier to read data from the memory cell 102-0˜102-n. In FIG. 12, the read circuit 116 illustrates the single-ended input circuit. In this case, in order to prevent a malfunction, it is necessary to design an equivalent load of a pair of bit lines blx_a and bl_a and bit lines blx_b and bl_b, which are connected to the memory cell 102-0˜102-n, as much as possible. Therefore, as depicted by FIG. 12, wiring lengths of pairs of bit lines that are connected to the memory cell 102-0˜102-n and the number of connected memory cells, has been designed to be symmetrical to.
Further, as depicted by the conventional example in FIG. 12, in order to speed up, the pair of the bit lines (blx_a and bl_a, and blx_b and bl_b) is divided between the memory cell array so as to be equivalent.